The present invention relates to a semiconductor integrated circuit, and more particularly to a switching circuit.
In a field of circuits for use in portable telecommunication equipment, lowering electric power is significantly required. In general, obstacles to lowering electric power of electronic equipment are MOS transistors (hereinafter, referred to as xe2x80x9cMOSxe2x80x9d) requiring large transconductance gm among components of the electronic equipment and an inverter or other logical gates. For example, in portable telecommunication equipment, a switch (hereinafter, referred to as xe2x80x9canalog switchxe2x80x9d) formed by the MOS is used for switching an input-output section for voice or other analog data, thereby obstructing lowering electric power.
As an example, a description will be made below for a semiconductor integrated circuit comprising an analog switch used for portable telecommunication equipment and its driver by referring to FIG. 8. A semiconductor integrated circuit 500, as shown in FIG. 8, comprises an analog switch 510 for switching an input-output section for analog data and a driver 520 for driving the analog switch 510.
The analog switch 510 comprises a P-channel MOS transistor (hereinafter, referred to as xe2x80x9cPMOSxe2x80x9d) M1 and an N-channel MOS transistor (hereinafter, referred to as xe2x80x9cNMOSxe2x80x9d) M2. A source of the PMOS M1 and a drain of the NMOS M2 are connected to an input terminal T1 to which analog data is inputted. A drain of the PMOS M1 and a source of the NMOS M2 are connected to an output terminal T2 to which analog data is outputted. An analog switch 510 having this configuration is also referred to as a transfer gate and widely used for a formation of a switched capacitor filter (SCF) circuit or of an integrating circuit.
The driver 520 comprises a control signal input terminal T3 to which a control signal is inputted for driving the analog switch 510, inverters INV1 and INV2 connected in series to the input terminal T3, and an inverter INV3 connected to the input terminal T3 and connected in parallel to the inverters INV1 and INV2. An output of the inverters INV1 and INV2 connected in series is connected to a gate G1 of the PMOS M1. An output of the INV3 is connected to a gate G2 of the NMOS M2. A signal inputted to the input terminal T3 is a supply voltage VDD at an H level or a ground voltage GND at an L level.
Logical levels are inverted between an output of the inverter INV2 and an output of the inverter INV3 which are outputs of the driver 520. Normally an output of an inverter is at either the supply voltage VDD or the ground voltage GND, and therefore the supply voltage VDD is applied to one of the gate G1 of the PMOS M1 to which the output of the inverter INV2 is applied and the gate G2 of the NMOS M2 to which the output of the inverter INV3 is applied, while the ground voltage GND is applied to the other.
For example, if the input terminal T3 is at the supply voltage VDD, the gate G1 of the PMOS M1 is at the supply voltage VDD and the gate G2 of the NMOS M2 is at the ground voltage GND, and therefore the analog switch 510 is not driven. If the input terminal T3 is at the ground voltage GND, the gate G1 of the PMOS M1 is at the ground voltage GND and the gate G2 of the NMOS M2 is at the supply voltage VDD, and therefore the analog switch 510 is driven.
As described above, outputs of the inverters are at the supply voltage VDD or at the ground voltage GND. The transconductance gm of the MOS in this condition will be considered below. To consider the transconductance gm, drain current ID is described, first.
The drain ID of the MOS is expressed by the following equation (equation 1):
ID=xcex2(VGSxe2x88x92VT)2/2xe2x80x83xe2x80x83(1)
where VGS is a gate-to-source voltage (also simply referred to as xe2x80x9cgate voltagexe2x80x9d), VT is a threshold voltage, and xcex2 is a constant proportional to dimensions of an MOS determined according to an effective channel length and an effective channel width of the MOS.
If the current ID expressed by the equation (1) is differentiated by the gate voltage VGS, the following equation is obtained:
gm=dID/dVGS=xcex2(VGSxe2x88x92VT)xe2x80x83xe2x80x83(2)
The characteristics of the MOS are represented by using the drain current ID or the transconductance gm. According to the equation (1) or (2), it is understood that the drain current is proportional to a square of the gate voltage VGS and that the transconductance gm is proportional to the gate voltage VGS.
In the semiconductor integrated circuit 500, the gate voltage VGS is equal to the supply voltage VDD, and therefore the transconductance gm between the terminal T1 and the terminal T2 is decreased together with a reduction of the supply voltage VDD. Additionally in the above circuit configuration, it is understood that the transconductance gm of the analog switch is decreased when the supply voltage VDD reaches about the same voltage as (PMOS M1 threshold value VTp)+(NMOS M2 threshold value VTn) according to the equation (2).
Consideration will be given below for a case in which the supply voltage VDD is decreased from 2.0 V to 1.8 V when the threshold voltage VTp of the PMOS M1 is xe2x88x920.8 V and the threshold voltage VTn of the NMOS M2 is 0.8 V, for example. If the supply voltage VDD is 2.0 V, (VGSxe2x88x92VTp ) of the PMOS M1 equals xe2x88x921xe2x88x92(xe2x88x920.8)=xe2x88x920.2 (V) and (VGSxe2x88x92VTn) of the NMOS M2 equals 1xe2x88x920.8=0.2 (V). Subsequently when the supply voltage VDD is decreased to 1.8 V, (Vgsxe2x88x92VTp) of the PMOS M1 equals xe2x88x920.9xe2x88x92(xe2x88x920.8)=xe2x88x920.1 (V) and (Vgsxe2x88x92VTn) of the NMNOS M2 equals 0.9xe2x88x920.8=0.1 (V).
At this moment, as described above, the drain current ID of the MOS is proportional to a square of the gate voltage VGS and the transconductance gm is proportional to the gate voltage VGS, and therefore if the supply voltage VDD is lowered from 2V to 1.8 V, the drain current ID is decreased to (0.1/0.2)2=25(%) and the transconductance gm is decreased to (0.1/0.2)=50 (%).
As described above, when the supply voltage VDD is decreased to lower the voltage and the supply voltage VDD approaches (the threshold value VTp of the PMOS M1) plus (the threshold value VTn of the NMOS M2), it is required to secure the drain current ID and the transconductance gm of the MOS forming the analog switch. As a means for securing the transconductance gm, there is a method of increasing dimensions of the MOS to increase the constant xcex2 in the equation (2).
Increasing the dimensions of the MOS, however, increases a capacity among the gate, the drain, and the source, thereby increasing injected electric charges to generate big switching noises. Therefore, there has been a limitation on securing the transconductance gm by increasing the dimensions of the MOS.
It is an object of the present invention to provide a semiconductor integrated circuit capable of achieving drain current and transconductance required for driving an analog switch even after lowering a supply voltage.
In order to accomplish the above object, the present invention provides a semiconductor integrated circuit comprising a transistor for a switch for transmitting an input signal given to one terminal to the other terminal according to a voltage given to a gate electrode, a boosting section for generating a higher voltage than a supply voltage, and an output section for giving the voltage generated by the boosting section to the gate electrode of the transistor for a switch.